diff options
Diffstat (limited to 'Software/pinlock.asm')
| -rw-r--r-- | Software/pinlock.asm | 373 |
1 files changed, 309 insertions, 64 deletions
diff --git a/Software/pinlock.asm b/Software/pinlock.asm index ba12dc9..e2204bf 100644 --- a/Software/pinlock.asm +++ b/Software/pinlock.asm @@ -2,29 +2,30 @@ .def tmp0 = r16 .def par0 = r17 .def par1 = r18 -.def cnt = r19 -.def tmp1 = r20 -.def tmp2 = r21 -.def ret0 = r22 -.def ret1 = r23 +.def tmp1 = r19 +.def tmp2 = r20 +.def ret0 = r21 +.def ret1 = r22 +.def par2 = r23 +.def par3 = r24 +.def par4 = r25 +.def ret2 = r26 +.def heart = r27 init: - ldi tmp0, HIGH(RAMEND) - out SPH, tmp0 - ldi tmp0, LOW(RAMEND) - ldi par0, 0xFF - ldi par1, 0xFF - rcall wait - out SPL, tmp0 - ldi tmp0, 0b11111111 - out DDRA, tmp0 - ldi tmp0, 0b11111111 - out DDRB, tmp0 - ldi tmp0, 0b11101100 - out DDRD, tmp0 - ldi tmp0, 0b00000000 - out PORTD, tmp0 - + ldi tmp0, HIGH(RAMEND) + out SPH, tmp0 + ldi tmp0, LOW(RAMEND) + out SPL, tmp0 + ldi tmp0, 0b11111111 + out DDRA, tmp0 + ldi tmp0, 0b11111111 + out DDRB, tmp0 + ldi tmp0, 0b11101100 + out DDRD, tmp0 + ldi tmp0, 0b00000000 + out PORTD, tmp0 + ldi heart, 0 ldi par0, 0 ldi par1, 0 rcall display @@ -37,22 +38,143 @@ init: ldi par0, 3 ldi par1, 3 rcall display + ldi par0, 0xFF + rcall status +stop: + rjmp stop + rjmp main -main: - ldi par0, 0b11111111 +debug_heart: + push par0 + push par1 + push par2 + inc heart + ldi par0, 3 + mov par1, heart + rcall display + mov par0, heart rcall status - rjmp [tmp0] + ldi par0, 0xFF + ldi par1, 1 + ldi par2, 1 + rcall wait + pop par2 + pop par1 + pop par0 + ret + +main: + rcall debug_heart + rcall input + mov par1, ret0 + lsr par1 + lsr par1 + lsr par1 + lsr par1 + ldi par0, 0 + rcall display + mov par1, ret0 + andi par1, 0x0F + ldi par0, 1 + rcall display + mov par1, ret1 + lsr par1 + lsr par1 + lsr par1 + lsr par1 + ldi par0, 2 + rcall display + mov par1, ret1 + andi par1, 0x0F + ldi par0, 3 + rcall display + rjmp main wait: - mov tmp0, par0 - dec par0 - nop - brne wait - mov par0, tmp0 - dec par1 - nop - brne wait - ret + push tmp0 + push tmp1 + mov tmp0, par0 + mov tmp1, par1 +wait_loop: + dec tmp0 + nop + brne wait_loop + mov tmp0, par0 + dec tmp1 + brne wait_loop + mov tmp0, par0 + mov tmp1, par1 + dec tmp2 + brne wait_loop + pop tmp1 + pop tmp0 + ret + +; Output bits to shift register. +; Parameters: +; par0 = Bits +; par1:par2 = Call address to set 0 +; par3:par4 = Call address to set 1 +; Returns: +; None +shift_out: + push par0 + push tmp0 + ldi tmp0, 8 +shift_out_loop: + sbrs par0, 0 + rjmp shift_out_low + rjmp shift_out_high +shift_out_low: + mov r31, par1 + mov r30, par2 + icall + rjmp shift_out_end +shift_out_high: + mov r31, par3 + mov r30, par4 + icall + rjmp shift_out_end +shift_out_end: + lsr par0 + dec tmp0 + brne shift_out_loop + pop tmp0 + pop par0 + ret + +; Input bits from shift register. +; Parameters: +; par0:par1 = Call address for one clock cycle +; par2:par3 = Call address to read serial shift in bit +; Returns: +; ret0 = Read bits +shift_in: + push tmp0 + ldi tmp0, 8 + ldi ret0, 0 +shift_in_loop: + lsl ret0 + mov r31, par0 + mov r30, par1 + icall + mov r31, par2 + mov r30, par3 + icall + cpi ret2, 0 + breq shift_in_low + rjmp shift_in_high +shift_in_low: + cbr ret0, 0 + rjmp shift_in_end +shift_in_high: + sbr ret0, 0 + rjmp shift_in_end +shift_in_end: + dec tmp0 + brne shift_in_loop + pop tmp0 + ret ; Output the status ; Parameters: @@ -60,27 +182,36 @@ wait: ; Returns: ; None status: - ldi tmp0, 1 -status_loop: - mov tmp1, par0 - and tmp1, tmp0 - cp tmp0, tmp1 - breq status_set - ldi tmp1, 0b00111111 - out PORTD, tmp1 - ldi tmp1, 0b10111111 - out PORTD, tmp1 - rjmp status_end -status_set: - ldi tmp1, 0b01111111 - out PORTD, tmp1 - ldi tmp1, 0b11111111 - out PORTD, tmp1 - rjmp status_end -status_end: - lsl tmp0 - cpi tmp0, 0 - brne status_loop + push par1 + push par2 + push par3 + push par4 + ldi par1, HIGH(status_low) + ldi par2, LOW(status_low) + ldi par3, HIGH(status_high) + ldi par4, LOW(status_high) + rcall shift_out + pop par1 + pop par2 + pop par3 + pop par4 + ret +status_low: + push tmp2 + in tmp2, PORTD + cbr tmp2, 6 + rjmp status_clk +status_high: + push tmp2 + in tmp2, PORTD + sbr tmp2, 6 + rjmp status_clk +status_clk: + cbr tmp2, 7 + out PORTD, tmp2 + sbr tmp2, 7 + out PORTD, tmp2 + pop tmp2 ret ; Display the digit on a given display. @@ -90,6 +221,8 @@ status_end: ; Returns: ; None display: + push tmp0 + push tmp1 mov tmp0, par1 andi tmp0, 0x0F cpi par0, 0 @@ -100,19 +233,19 @@ display: breq display_2 cpi par0, 3 breq display_3 - ret + rjmp display_end display_0: in tmp1, PORTA andi tmp1, 0xF0 or tmp1, tmp0 out PORTA, tmp1 - ret + rjmp display_end display_1: in tmp1, PORTB andi tmp1, 0xF0 or tmp1, tmp0 out PORTB, tmp1 - ret + rjmp display_end display_2: in tmp1, PORTA andi tmp1, 0x0F @@ -122,7 +255,7 @@ display_2: lsl tmp0 or tmp1, tmp0 out PORTA, tmp1 - ret + rjmp display_end display_3: in tmp1, PORTB andi tmp1, 0x0F @@ -132,6 +265,10 @@ display_3: lsl tmp0 or tmp1, tmp0 out PORTB, tmp1 + rjmp display_end +display_end: + pop tmp1 + pop tmp0 ret ; Read the input buttons. @@ -142,10 +279,118 @@ display_3: ; ret1 = 789C*0#D input: ; Write selection rows - ldi tmp0, 1 - ldi tmp1, 1 + ldi par0, 1 input_loop: - mov tmp2, tmp0 - and tmp2, tmp1 - cp tmp1, tmp2 - breq input_set + ldi par1, HIGH(input_write_low) + ldi par2, LOW(input_write_low) + ldi par3, HIGH(input_write_high) + ldi par4, LOW(input_write_high) + rcall shift_out + rjmp input_read +input_write_low: + push tmp0 + in tmp0, PORTD + cbr tmp0, 3 + cbr tmp0, 5 + out PORTD, tmp0 + sbr tmp0, 5 + out PORTD, tmp0 + pop tmp0 + ret +input_write_high: + push tmp0 + in tmp0, PORTD + sbr tmp0, 3 + cbr tmp0, 5 + out PORTD, tmp0 + sbr tmp0, 5 + out PORTD, tmp0 + pop tmp0 + ret +input_read: + push tmp0 + in tmp0, PORTD + sbr tmp0, 2 + out PORTD, tmp0 + cbr tmp0, 2 + out PORTD, tmp0 + sbr tmp0, 2 + out PORTD, tmp0 + push par0 + ldi par0, HIGH(input_read_clk) + ldi par1, LOW(input_read_clk) + ldi par2, HIGH(input_read_bit) + ldi par3, LOW(input_read_bit) + push ret0 + rcall shift_in + mov tmp0, ret0 + pop ret0 + pop par0 + ; par0 = row + ; tmp0 = col + mov tmp1, par0 + andi tmp1, 0x03 + cpi tmp1, 0 + breq input_read_rows_01 + mov tmp1, par0 + lsr tmp1 + lsr tmp1 + rjmp input_read_rows_23 +input_read_clk: + push tmp1 + in tmp1, PORTD + cbr tmp1, 5 + out PORTD, tmp1 + sbr tmp1, 5 + out PORTD, tmp1 + pop tmp1 + ret +input_read_bit: + in ret2, PORTD + andi ret2, 0b00010000 + ret +input_read_rows_01: + andi tmp1, 1 + cpi tmp1, 1 + breq input_read_row_0 + rjmp input_read_row_1 +input_read_row_0: + andi ret0, 0xF0 + rjmp input_read_rows_01_end +input_read_row_1: + andi ret0, 0x0F + lsl tmp0 + lsl tmp0 + lsl tmp0 + lsl tmp0 + rjmp input_read_rows_01_end +input_read_rows_01_end: + or ret0, tmp0 + rjmp input_end +input_read_rows_23: + andi tmp1, 1 + cpi tmp1, 1 + breq input_read_row_2 + rjmp input_read_row_3 +input_read_row_2: + andi ret1, 0xF0 + rjmp input_read_rows_23_end +input_read_row_3: + andi ret1, 0x0F + lsl tmp0 + lsl tmp0 + lsl tmp0 + lsl tmp0 + rjmp input_read_rows_23_end +input_read_rows_23_end: + or ret1, tmp0 + rjmp input_end +input_end: + pop tmp0 + lsl par0 + andi par0, 0x0F + cpi par0, 0 + brne input_loop_j + ret +input_loop_j: + rjmp input_loop |