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AgeCommit message (Collapse)Author
2020-06-21GeneralLeonard Kugis
Added real world units for capacitors and resistors.
2020-02-04LayoutLeonard Kugis
Optimizations. Changed packaging of some parts.
2019-11-25Larger pin headersLeonard Kugis
2019-11-25Schematic, LayoutLeonard Kugis
Changed Barrel Jack pinout. Layout components placed.
2019-11-24Layout not fitting yet, needs improvementLeonard Kugis
2019-11-24Begin associationsLeonard Kugis
2019-11-24GeneralLeonard Kugis
Added references to all elements.
2019-11-20UARTLeonard Kugis
Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
2019-11-19GeneralLeonard Kugis
Removed too many test points.
2019-11-13Schematic, generalLeonard Kugis
Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
2019-11-13Schematic, main, generalLeonard Kugis
Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
2019-11-07Schematic, StatusLeonard Kugis
Separated logic IO from power with transistors.
2019-11-07Schematic, PinoutLeonard Kugis
Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
2019-11-04structure, buttons, statusLeonard Kugis
Implemented hierarchy. Added button interface. Added status interface.
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