From 45f4b24e5b0138c241b7fa9384d5768582769c55 Mon Sep 17 00:00:00 2001
From: Leonard Kugis <leonard@kug.is>
Date: Wed, 13 Nov 2019 14:13:18 +0100
Subject: Schematic, main

Added pull resistors to every pin of uC.
Restructured main schematic.
Added ISP interface.
---
 PinLock-cache.lib | 41 ++++++++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 13 deletions(-)

(limited to 'PinLock-cache.lib')

diff --git a/PinLock-cache.lib b/PinLock-cache.lib
index 0d6a264..1213abc 100644
--- a/PinLock-cache.lib
+++ b/PinLock-cache.lib
@@ -94,6 +94,34 @@ X e 9 500 -100 200 L 50 50 1 0 C
 ENDDRAW
 ENDDEF
 #
+# Connector_AVR-ISP-6
+#
+DEF Connector_AVR-ISP-6 J 0 40 Y Y 1 F N
+F0 "J" 0 400 50 H V L CNN
+F1 "Connector_AVR-ISP-6" 0 -300 50 H V L CNN
+F2 "" -250 50 50 V I C CNN
+F3 "" -1275 -550 50 H I C CNN
+$FPLIST
+ IDC?Header*2x03*
+ Pin?Header*2x03*
+$ENDFPLIST
+DRAW
+S -105 -220 -95 -250 0 1 0 N
+S -105 350 -95 320 0 1 0 N
+S 250 -95 220 -105 0 1 0 N
+S 250 5 220 -5 0 1 0 N
+S 250 105 220 95 0 1 0 N
+S 250 205 220 195 0 1 0 N
+S 250 350 -250 -250 0 1 10 f
+X MISO 1 400 200 150 L 50 50 1 1 P
+X VCC 2 -100 500 150 D 50 50 1 1 W
+X SCK 3 400 0 150 L 50 50 1 1 P
+X MOSI 4 400 100 150 L 50 50 1 1 P
+X ~RST 5 400 -100 150 L 50 50 1 1 P
+X GND 6 -100 -400 150 U 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
 # Connector_AVR-JTAG-10
 #
 DEF Connector_AVR-JTAG-10 J 0 40 Y Y 1 F N
@@ -460,17 +488,4 @@ X 2 2 200 0 100 L 50 50 0 1 P
 ENDDRAW
 ENDDEF
 #
-# power_GND
-#
-DEF power_GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "power_GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
 #End Library
-- 
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