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-rw-r--r--Presentation/presentation.tex13
1 files changed, 7 insertions, 6 deletions
diff --git a/Presentation/presentation.tex b/Presentation/presentation.tex
index f4ac0c7..eb7eae8 100644
--- a/Presentation/presentation.tex
+++ b/Presentation/presentation.tex
@@ -310,9 +310,9 @@ backend=biber,
\begin{itemize}
\item Optimizes per-activation formula:
\begin{align}
- b_i = \text{ReLU}(\sum\limits_{j=0}^{n-1} W_{ij} a_j) \overset{!}{=} \text{ReLU}(\sum\limits_{j \in X_i \cap Y} S[I_{ij}] a_j)
+ b_i = f(\sum\limits_{j=0}^{n-1} W_{ij} a_j) \overset{!}{=} \text{ReLU}(\sum\limits_{j \in X_i \cap Y} S[I_{ij}] a_j)
\end{align}
- \item $X_i$: Set of columns with $W_{ij} \neq 0$
+ \item $X_i$: Set of columns, skipping $W_{ij} = 0$
\item $Y$: Set of indices in $a$ for which $a_j \neq 0$
\item $I_{ij}$: 4-bit index
\item $S$: Shared lookup table
@@ -364,7 +364,8 @@ backend=biber,
\hfill
\begin{minipage}{0.59\linewidth}
\begin{itemize}
- \item Pointers to columns $W_j$ are stored in seperate SRAM banks (start/end)
+ \item Pointers to columns $W_j$ are stored alternating in seperate SRAM banks
+ \item Start- and end-pointers are read out simultaneously
\end{itemize}
\end{minipage}
\end{frame}
@@ -398,7 +399,7 @@ backend=biber,
\hfill
\begin{minipage}{0.59\linewidth}
\begin{itemize}
- \item Receives column vector $v$, destination accumulator register index $x$ and activation value $a_j$
+ \item Receives column vector $v$, absolute destination accumulator register index $x$ and activation value $a_j$
\item Calculates $b_x = b_x + v \cdot a_j$
\item Accumulates indices $x$ and forwards real target address
\end{itemize}
@@ -483,12 +484,12 @@ backend=biber,
\end{itemize}
\item Combination with other optimization methods
\begin{itemize}
- \item In-Memory calculation
+ \item In-Memory computation
\item Approximating circuits
\end{itemize}
\item Optimize hardware itself
\begin{itemize}
- \item Different storage technologies (e.g. ReRAM)
+ \item Different storage technologies (e.g. Memristors)
\end{itemize}
\end{itemize}
\end{frame}